dts: arm: stm32h7 MPU attribute for the external Memory #68593
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dts/arm/st/h7/stm32h7.dtsi
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This will break #57467 which required a strongly ordered memory.
If this is incompatible, this means we should define 2 different targets ("variants" in hwmv2) which would define different zephyr,memory-attr depending if memory is expected to be used in XIP or storage
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The https://github.com/zephyrproject-rtos/zephyr/blob/main/include/zephyr/arch/arm/mpu/arm_mpu_v7m.h
sets the REGION_EXTMEM_ATTR to be STRONGLY_ORDERED_SHAREABLE
And the Memory region shareability and cache policies for the stm32h7 and stm32F7 (AN4839)
defines the 0x80000000-0x9FFFFFFF range Non-shareable Write-through
--> Could this difference explain the pb ?
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The AN4760 and AN4861 propose to define the entire region as strongly ordered, non-cacheable, no access, execute never (while memory-mapped mode is not enabled). The ATTR_MPU_EXTMEM more or less follows, and it is ok for non-xip targets.
However, with xip, the attributes should be modified or an extra xip region shall be defined inside the extmem region. That region should start at the mapped memory address with the size of the slot.
The xip region attributes might differ for bootloader (region can stay as strongly ordered, non-cacheable, execute never, but require rw access) and application (region follows RM and is defined as normal, non-shareable, and require to execute and read with optional write access).
Some configurations are not defined within current arm_mpu_v7m.
The MPU usage in STM32 with ARM Cortex®-M7 is quite helpful.
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OK, keeping the ATTR_MPU_EXTMEM for the entire EXTMEM region:
which can be quad-spi or octo-spi depending on the stm32h7x device.
addressable memory space is 0x90000000 - 0x9FFFFFFF
The stm32h7a/b has another external memory area at 0x70000000 - 0x7FFFFFFF
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Define the MPU attribute to be ATTR_MPU_EXTMEM for the external region (qspi- or octo-spi NOR flash) starting at 0x90000000 of the stm32h7 serie. A XiP region should be Included inside with attribute ATTR_MPU_IO, to access the external memory in XIP. The stm32h7a/h7b serie as another external area at 0x70000000. Signed-off-by: Francois Ramu <[email protected]>
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Define the MPU attribute to be ATTR_MPU_IO for the qspi region, starting at 0x90000000 of the stm32h7 serie. That will allow XiP on the external NOR flash octo-quad spi.
This change will prepare the XiP on external NOR flash with stm32h7 boards